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ISL6801
Data Sheet July 25, 2005 FN9087.2
High Voltage Bootstrap High Side Driver
The ISL6801 is a single monolithic, inverting bootstrap driver. Its floating Level Shifter Section is optimized for the control of N-Channel Power MOSFETs in high side configurations with Bus Voltages up to 120VDC from a 5V Controller Output. It features two output stages pinned out separately to allow independent control of rise and fall times. To ensure static DC operation an integrated recharge path charges the bootstrap cap while the driver is switched off. A pull-up resistor forces the input low when no control signal is applied. The supply voltage is monitored to guarantee faultless operation at start-up.
Features
* Single Bootstrap High Side Driver * Bootstrap Supply Max Voltage. . . . . . . . . . . . . . . 120VDC * Peak Output Drive Current. . . . . . . . . . . . . . . . . . . 200mA * Switching Frequency . . . . . . . . . . . . . . . . . . . . . . . 100kHz * Active Low Input * Separate Reset Input * Recharge Path for Static Operation * Separate High and Low Gate Drive Outputs Allow Independent Turn ON/OFF Time Control * Supply Undervoltage Protection
Ordering Information
PART NUMBER ISL6801AB ISL6801AB-T TEMP. RANGE (oC) -40 to 125 -40 to 125 PACKAGE 8 Ld SOIC 8 Ld SOIC Tape and Reel PKG. DWG. # M8.15 M8.15
* Space Saving SO-8 Package * Wide Operating Temperature Range
Applications
* Driver for N-Channel MOSFETs in High Side Configurations that Control Ground Referenced Loads * Drives Solenoids, Motors, Relays and Lamps in Automotive Applications
Pinout
SL6801AB (SOIC) TOP VIEW
VCC IN GND RES
1 2 3 4
8 7 6 5
VB HOH HOL VS
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 321-724-7143 | Intersil (and design) is a registered trademark of Intersil Americas Inc. Copyright (c) Intersil Americas Inc. 2002, 2005. All Rights Reserved All other trademarks mentioned are the property of their respective owners.
ISL6801 Typical Application Block Diagram
+150VDC MAX BOOTSTRAP SUPPLY VCC HOH IN CONTROLLER INPUT LOGIC LEVEL SHIFTER HOL VS VB
RES
RECHARGE PATH
LOAD
ISL6801
Functional Block Diagram
VCC UV DETECT IN & RES ON DELAY OFF & LEVEL SHIFTER OUTPUT
VB
HOH
HOL
GND
VS
Pin Descriptions
PIN NUMBER 1 2 3 4 5 6 7 8 SYMBOL VCC IN GND RES VS HOL HOH VB Driver Supply, Typical 5.0V Driver Control Signal Input Ground Driver Enable Signal Input (`RESET') MOSFET Source Connection MOSFET Gate Low Connection MOSFET Gate High Connection Driver Output Stage Supply DESCRIPTION
NOTE: The HOL and HOH are the low respective high gate drive output pins. The turn on and turn off time of the external MOSFET could be controlled by using different resistance values for high and low signal.
2
ISL6801
Absolute Maximum Ratings
Supply Voltage, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16V Driver Output Stage Voltage, VB (Referred to GND) . . . . . . . . .130V Source Reference Voltage, VS (-5V for 0.5ms, MOSFET Off). . . . . . . . . . . . . . . . . . . . (Min) -1.5V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . (Max) 120V ESD Rating, VESD Human Body Model . . . . . . . . . . . . . . . . . . . . . . . . . . . (Min) 820V (Per MIL-STD-883 Method 3015.7)
Thermal Information
Thermal Resistance (Typical, Note 1)
JA (oC/W)
SOIC Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 Maximum Junction Temperature (Plastic Package) . . . . . . . .150oC Maximum Storage Temperature Range . . . . . . . . . -55oC to 150oC Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . .245oC (SOIC Lead Tips Only)
Operating Conditions
Temperature Range. . . . . . . . . . . . . . . . . . . . . . . . . -40oC to 125oC Supply Voltage Range (Max) . . . . . . . . . . . . . . . . . . . . 4.5V to 6.5V
CAUTION: Stresses above those listed in "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTE: 1. JA is measured with the component mounted on a high effective thermal conductivity test board in free air. See Tech Brief TB379 for details.
Electrical Specifications
PARAMETER Operating Temperature Range Source Reference Voltage
All values are over full temperature range. SYMBOL TA VS -1.8V Continuous, VB/VOH must stay low, IN = 0V, RES = 5V, VCC = 4.5V and 6.5V, VB = 5V and 12V, (Load R = 50, C = 6.8nF) TA = -40 to 125oC TEST CONDITIONS MIN -40 -1.5 TYP MAX 125 120 UNITS
oC
V
Supply Voltage (Note 2) Driver Output Supply
VCC VVB - VS VVB - GND Ident. to VGS of MOSFET Device Functional Guaranteed by Design
4.5 4.0 2.0 100 Sink/Source Current VB = 5V and 16V, 100ns Sink/Source Current Continuous IN at H, IHO = 1mA, VB-VS = 5V and 16V IN at H, IHO = 100mA IN at L, IHO = 1mA, VB-VS = 5V and 16V IN at L, IHO = 100mA at VCC = 5.0V, RES = 5V, Output Trigger Level: 3.5V ON at VB = 5V, 1.0V OFF at VB = 16V, Input 2.5V (Load R = 50, C = 6.8nF) VB-VS = 5V and 16V, (Load R = 50, C = 6.8nF) VB-VS = 5V (Load R = 50, C = 6.8nF) VB-VS = 16V 6.5 -
8.5 200 8 1.0
6.5 16.0 500 0.3 2.2 0.5 2.2 3.0
V V V kHz V/s mA mA V V V V s
Switching Frequency Voltage Transconductance (Note 3) Peak Gate Drive Current Continuous Gate Drive Current (Note 3) Gate Drive Level LOW Gate Drive Level LOW Gate Drive Level HIGH Gate Drive Level HIGH Total IN to Output Delay (Figure 1)
f dVs/dt IHOpeak IHOcont VHOL, VS VHOL, VS VVB, HOH VVB, HOH tdIN-HOH, L
Total RES to Output Delay (Figure 2) Output Rise/Fall Times
tdRES - HOH, L tHOH, L Fall/Rise
-
1.0 100 200 100
3.0 500 500 210 (Note 5)
s ns ns mV
VB Drop Voltage (Figure 4, Note 4)
VBDROP
VB-VS = 9.0V, C100 = 1F, (Load R = 50, C = 6.8nF)
3
ISL6801
Electrical Specifications
PARAMETER VB Input Current (Note 6) All values are over full temperature range. (Continued) SYMBOL IVB TEST CONDITIONS Static Current, VB-VS = 8.5V, VCC = 5V, IN = 0V, RES = 5V, (Load R = 50, C = 6.8nF) Static Current, VB-VS = 8.5V, VCC = 5V, IN = 0V, RES = 0V, (Load R = 50, C = 6.8nF) at VCC = 4.5V and 6.5V (Load R = 50, C = 6.8nF) VCC = 4.5V and 6.5V VCC = 4.5V and 6.5V VCC = 4.5V and 6.5V VCC = 4.5V and 6.5V at VCC = 5.0V, RES = 5V, IN = 0V, VB = 12V at VCC = 5.0V, RES = 5V, IN = 0V, VB = 12V at Logic LOW Response HIGH VCC to GND, Incl. Hyst. VB = VS = HOH = HOL = 7V, RES = 5V, IN = 5V, VCC = 4.5V and 6V MIN 300 TYP 750 MAX 875 UNITS A
VB Input Current
IVB
100
550
700
A
Driver Supply Current Input Threshold LOW (Note 7) Input Threshold HIGH (Note 7) Enable Threshold LOW (Note 7) Enable Threshold HIGH (Note 7) Input Impedance at IN Input Impedance at RES Logic Input Current at RES (Note 8) Undervoltage Shutdown Threshold Recharge Resistance (Note 9) Recharge Turn On Delay (Note 9) Recharge Turn Off Delay Recharge Path Voltage Drop
IVCC INLOW INHIGH RESLOW RESHIGH RIN RRES IRES VUV Rrecharge tRechargeON tRechargeOFF Vdrop Recharge
1.4 1.4 60 60 -0.1 70 7 -
1.2 100 100 3.5 170 10 -
2.5 3.0 3.0 170 170 1.0 350 15 1.5 0.8 3.5
mA V V V V k k mA V s s V V
at a Constant Current of 1.0mA at a Constant Current of 10mA
-
NOTES: 2. Shutdown between 3.5V and 4.5V. 3. Parametric limits are guaranteed by design, but not tested in production. 4. The drop voltage is caused by VB to VS current flow during switching. See Figure 3. 5. Assuming 3s switching overlap, time delay use at testing 100s. 6. External MOSFET ON or OFF. 7. Input and Enable thresholds tested at VCC = 4.5V and 6.5V, VB = 12V, VS = 0V, IN at 0V, Response RES at 5.0V. 8. The defined values are to be considered as a maximum allowed value. The input stage does not need to have sink or source capability. 9. The recharge path has to withstand transients in the 120V range for approximately 1s while injector turn off, causing high power dissipation in the resistor.
4
ISL6801 Timing Diagrams
IN RES 90% VS HOH, L 90%
10% tdIN-HOH, L tdIN-HOH, L ON tHOH, Lrise tHOH, Lfall
10%
RECHARGE
OFF
tRechargeOFF
tRechargeON
FIGURE 1. INPUT/OUTPUT TIMING DIAGRAM
IN
RES
HOH, L
tdRES-HOH, L
tdRES-HOH, L
FIGURE 2. RESET TIMING DIAGRAM
VB Drop Voltage Test
Ig Ig IN 1 VCC IN 2 IN 3 GND 4 RES ISL6801 VB-VS VB 8 50R HOH 7 50R HOL 6 7V VS 5 6n8 1 RES
OFF 0A
VBDROP
BREAK BEFORE MAKE
FIGURE 3. VB DROP VOLTAGE TEST CIRCUIT
FIGURE 4. VB DROP VOLTAGE DIAGRAM
5
ISL6801 Small Outline Plastic Packages (SOIC)
N INDEX AREA E -B1 2 3 SEATING PLANE -AD -CA h x 45o H 0.25(0.010) M BM
M8.15 (JEDEC MS-012-AA ISSUE C)
8 LEAD NARROW BODY SMALL OUTLINE PLASTIC PACKAGE INCHES SYMBOL A
L
MILLIMETERS MIN 1.35 0.10 0.33 0.19 4.80 3.80 MAX 1.75 0.25 0.51 0.25 5.00 4.00 NOTES 9 3 4 5 6 7 8o Rev. 0 12/93
MIN 0.0532 0.0040 0.013 0.0075 0.1890 0.1497
MAX 0.0688 0.0098 0.020 0.0098 0.1968 0.1574
A1 B C D E

A1 0.10(0.004) C
e H h L N
0.050 BSC 0.2284 0.0099 0.016 8 0o 8o 0.2440 0.0196 0.050
1.27 BSC 5.80 0.25 0.40 8 0o 6.20 0.50 1.27
e
B 0.25(0.010) M C AM BS
NOTES: 1. Symbols are defined in the "MO Series Symbol List" in Section 2.2 of Publication Number 95. 2. Dimensioning and tolerancing per ANSI Y14.5M-1982. 3. Dimension "D" does not include mold flash, protrusions or gate burrs. Mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006 inch) per side. 4. Dimension "E" does not include interlead flash or protrusions. Interlead flash and protrusions shall not exceed 0.25mm (0.010 inch) per side. 5. The chamfer on the body is optional. If it is not present, a visual index feature must be located within the crosshatched area. 6. "L" is the length of terminal for soldering to a substrate. 7. "N" is the number of terminal positions. 8. Terminal numbers are shown for reference only. 9. The lead width "B", as measured 0.36mm (0.014 inch) or greater above the seating plane, shall not exceed a maximum value of 0.61mm (0.024 inch). 10. Controlling dimension: MILLIMETER. Converted inch dimensions are not necessarily exact.
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Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
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